This application relies for priority upon Korean Patent Application No. 2000-21646, filed on Apr. 24, 2000 and Korean Patent Application No. 2000-76373, filed on Dec. 14, 2000, the contents of which are herein incorporated by reference in their entirety.
The present invention relates generally to a flash memory, and more specifically to the optimization of threshold voltage distribution profiles of erased memory cells in a flash memory.
Flash memories, including electrically erasable and programmable read only memories (EEPROMs), offer advanced performance in reading and writing (or programming) data, as compared to other kinds of nonvolatile memories. Because of its high speed operation, flash memory is the preferred memory device for portable computing devices, cellular phones, digital still cameras, and similar equipment. A typical flash memory includes a plurality of memory cells formed in a matrix of rows and columns. Erasing the memory cells is generally performed for an entire memory cell array, called a block or sector, at the same time. Programming can be conducted for one or more memory cells at a time.
FIG. 1 illustrates a conventional flash memory cell. Referring to FIG. 1, a conventional flash memory cell includes a floating gate transistor 10 constructed of a source 14, a drain 16, a floating gate 22, and a control gate 26. The floating gate 22 is deposited on an oxide film 20 on a channel region 18 in a bulk substrate 12, and overlaps edges of the source 14 and drain 16 regions. The control gate 26 is formed over the floating gate 22. An intermediate insulation layer 24 is interposed between the control gate 26 and the floating gate 22 to isolate the gate layers. This intermediate insulation layer 24 may be formed, for example, of Oxe2x80x94Nxe2x80x94O (oxide-nitride-oxide).
In the flash memory, the control gates 26 of each of the various transistors 10 arranged in a row are connected to the same wordline in common. Similarly, the drain regions 16 of each of the transistors 10 arranged in a column are connected to the same bitline in common. The source regions 14 of each of the transistors 10 in the flash memory are connected to a common source line in common.
A typical programming operation in a flash memory device is accomplished by inducing a hot electron injection from the channel region 18, nearby the drain 16, to the floating gate 22. In order to cause the hot electron injection, the source 14 and substrate (or bulk) 12 are held at ground potential, while the control gate 26 is connected to a high positive voltage (Vg) of about 10V and the drain 16 is biased with a voltage of about 5xcx9c6V. A memory cell programmed in the manner just described has negative charges in its floating gate 22. This, in turn, increases its threshold voltage during a read operation.
In a read operation, the drain 16 is provided with a voltage of about 1V, while the control gate 26 is connected to a power supply voltage (i.e., about 5V) and the source is connected to 0V. Since the increased threshold voltage of the programmed memory cell acts as a blocking potential on the gate voltage during a read-out operation, the programmed cell is considered to be an xe2x80x9coffxe2x80x9d cell. The programmed (or xe2x80x9coffxe2x80x9d) cell, typically has a threshold voltage of between 6V and 8V, as indicated by the Programmed State voltage distribution profile shown in FIG. 2.
Erasing a flash memory cell is accomplished using the F-N (Fowler-Nordheim) tunneling effect. During an erasing operation, the control gate 26 is coupled to a high negative voltage of about xe2x88x928V, and the substrate (or bulk) 12 is connected to a high positive voltage of about 8xcx9c10V in order to induce the tunneling therebetween. Meanwhile, the drain 16 is conditioned at a high impedance state (or a floating state). A strong electric field is induced by the difference in voltage bias conditions between the control gate 26 and bulk region 12. This electric field causes electrons to be moved into the source 14. F-N tunneling normally occurs when an electric field of around 6xcx9c7MV/cm is developed across the thin insulating film 20 between the floating gate 22 and bulk region 12. The thin insulating film 20 separating the floating gate 22 and bulk region 12 typically has a thickness of less than 100 xc3x85. The erased cell has a lower threshold voltage, typically between about 1xcx9c3V, and is therefore sensed as an xe2x80x9conxe2x80x9d cell during a read operation.
In a typical flash memory cell array architecture, the bulk region (or substrate) 12 combines active regions of multiple memory cells, so that each of the memory cells formed in the same bulk region 12 are spontaneously erased at the same time. A unit of memory cells erased by a single erase operation is called a sector (or block). Sectors are configured by separating the bulk region. Each sector typically contains memory cells providing about 64K of memory.
Table 1 shows the different bias voltage levels applied to each of the various regions of a flash memory cell during the programming, erasing, and reading operation modes. In Table 1, control gate voltage is represented by Vg, drain voltage is represented by Vd, source voltage is represented by Vs, and bulk voltage is represented by Vb.
The control gate voltage Vg is supplied by a row decoder in the flash memory device. As shown in the table 1, the control gate voltage Vg varies according to the operation mode. Varying the control gate voltage Vg helps form the basic biasing conditions that establish the states of a selected memory cell. Control gate voltage Vg must be stabilized to secure reliability for the various operations.
Unfortunately, some problems exist with respect to the use of flash memories. FIG. 2 is a graph illustrating threshold voltage distribution profiles for a Programmed State and an Erased State of a flash memory. Referring to FIG. 2, after a conventional erasing operation has been performed on a block of memory cells, a group of those memory cells may have threshold voltages below a minimum desired threshold voltage value (e.g., 1V) representing an erasure state. The shaded region of the Erased State voltage distribution profile indicates the number of cells in this over-erased state and the undesirably low threshold voltage region in which they lie.
Over-erased cells can result from a difference in erasing speeds between the various memory cells belonging to a sector. In general, the erasing speed depends on a coupling ratio R. The coupling ratio R is determined by a relationship between a first capacitance Cono, between the floating gate 22 and the control gate 26, and a second capacitance Ctunnel, between the floating gate 22 and channel region 18. This ratio is determined according to the following equation:
R=Cono/(Cono+Ctunnel)
The first capacitance Cono is variable with the topology of the floating gate 22 and the thickness of the intermediate Oxe2x80x94Nxe2x80x94O insulation film layer 24. The second capacitance Ctunnel is affected by the thickness of the tunnel oxide film 20 and the width of the channel region 18. Ensuring the uniformity of both the tunnel oxide thickness and the width of the channel region 18 is important because the second capacitance Ctunnel has a significant effect on the coupling ratio. Providing uniformity between channel widths would significantly reduce over-erasing of the memory cells. Current manufacturing facilities, however, have been unable to sufficiently narrow or control channel width to overcome the problem of over-erasing., and uneven erasing speeds resulting in over-erased memory cells are therefore common.
The width of a threshold voltage distribution profile is called its xe2x80x9cactive width.xe2x80x9d As can be seen from the Erased State voltage distribution profile of FIG. 2, the presence of over-erased cells results in a wider distribution profile along the axis of threshold voltage (i.e., an increased active width). The active width of the Erased State voltage distribution profile is therefore directly related to the problem of over-erased memory cells, and correcting the problems from over-erasing of memory cells can be achieved by other means of narrowing the active width.
xe2x80x9cPre-programmingxe2x80x9d and xe2x80x9cpost-programmingxe2x80x9d are prior art methods of reducing the active width of a memory cell by preventing or curing over-erased memory cells. Under-programmed memory cells are programmed cells having threshold voltages below a predetermined minimum program voltage (e.g., 6V). In pre-programming, under-programmed cells are re-programmed until their voltages are at least above the minimum desired level. In post-programming, over-erased cells are cured by raising their threshold voltages above the lowest desired erased state voltage (e.g., 1V).
FIG. 3 is a flow chart illustrating a prior art erasure operation including both a pre-programming and post-programming step. Referring to FIG. 3, the erasure operation begins with a Pre-Program step to ensure that all programmed cells have a voltage above the minimum program voltage. The Main Erasure step is then carried out to erase each of the memory cells in the desired sector. After this main erasing step is completed, post-programming is carried out to correct any over-erased cells. Pre-programming and post programming are performed using the program bias voltages shown in Table 1.
The pre-programming step is outlined in more detail by the flow chart in FIG. 4. Referring to FIG. 4, during the pre-programming step, a programmed cell is put into a checking step S10 to verify whether it is positioned within a predetermined program state or not. If the threshold voltage of the programmed cell is less than the minimum voltage (e.g., 6V) established for a program state, a further programming operation S12 is performed for the under-programmed cell. This programming operation S12 repeats itself until the voltage is above the minimum established level. When the threshold voltage of the programmed cell reaches at least the minimum level, the pre-programming steps are then conducted for the next programmed cell. The pre-programming operation is terminated when the last programmed cell is verified as being programmed completely. After finishing the pre-programming operation, each of the programmed cells should have a threshold voltage equal to or greater than the minimum program voltage, and should thus be established as an xe2x80x9coffxe2x80x9d cell. The main erasing operation can then proceed.
FIG. 5 is a flow diagram illustrating the basic steps of the main erasure operation. Referring FIG. 5, the main erasing operation includes an erasing step S20 and a verifying step S22, which repeat themselves until all of the memory cells have threshold voltages of less than 3V. More specifically, an erasing operation S20 is performed on all of the cells in a sector using the biasing voltages shown in Table 1. An erasing verification operation S22 is then performed to ensure that each of the memory cell threshold voltages is below the maximum allowable voltage (e.g., 3V) for an erased memory cell. If any of the memory cells in the sector has a voltage higher than the maximum allowable level, the erasing step is performed again on all of the cells in the sector. Only after all of the memory cells are verified as having threshold voltages less than the maximum erased voltage level does the process proceed to the next step.
Referring again to FIG. 3, after the pre-programming and main erasing steps are completed, due to the remaining possibility of over-erased memory cells, a post-programming step must be carried out as well. In the post-programming step, the sources 14 and bulk 12 of erased cells are grounded, the control gates 26 are connected to a program voltage (10V), and the drains 16 are connected to a voltage of about 5xcx9c6V. The post-programming operation is generally the same as the pre-programming operation shown in FIG. 4, except that the electric field induced between the floating gate 22 and the channel region 18 during post-programming is weaker than that induced during pre-programming. Charges smaller than those of the pre-programming step are therefore settled into the floating gates 22 during post-programming.
Although the use of the pre-programming and post-programming steps in this method reduces the number of over-erased cells, the possibility of over-erased memory cells still exists. This is because the verification loop causes the erasing process to repeat erasing all of the cells in the sector even if only one of those memory cells is above the highest allowable erase threshold voltage. In other words, the erasing operation is repeated on all of the memory cells until the last one reaches a threshold voltage below the highest allowable erased voltage level. Thus, because memory cells with a higher coupling ratio R are erased faster than memory cells having a smaller ratio, the cells with higher ratios may become over-erased through repeated erasing operations. The greater the difference in erasure speeds between cells in a sector, the wider the active width of the distribution profile for that sector will be.
Specifically, through repeated erasing operations during the main erasure step, the fast-erased cells become situated in the low threshold voltage region, as represented by the shaded area of the Erased State distribution profile in FIG. 2. This low voltage region, or over-erased state, can be defined as below 0V or as below the minimum voltage level for an erased cell (e.g., 1V). Over-erasure can cause a read-out fail during a program verifying operation because the over-erased cells may be detected as an xe2x80x9conxe2x80x9d cell due to the low threshold voltages.
Further, during post-programming, when a voltage of 5xcx9c6V is applied to the drain 16 of a selected memory cell, the floating gate voltage Vf (where Vf=Rdxc3x97Vd) of a non-selected memory cell belonging to the column containing the selected memory cell is increased according to a drain coupling ratio Rd (where Rd=Cdrain/(Cono+Ctunnel)). If the floating gate voltage Vf is above a threshold voltage Vfg of the non-selected memory cell, an abnormal conductive state, called xe2x80x9cprogram failxe2x80x9d or xe2x80x9cdrain turn-onxe2x80x9d, arises in the non-selected memory cell. This drain turn-on effect can make the post-programming operation unavailable entirely or it can slow the post-programming operation down substantially. This phenomenon therefore serves as an important factor in determining the minimum value of the erased threshold voltages in the distribution profile.
The various aspects and embodiments of the present invention are intended to solve the foregoing problems.
One object is to provide a method of erasing memory cells that results in threshold voltages defined in a narrower active range.
It is another object to provide a method of erasing memory cells with erasing speeds that are uniformly controlled.
It is another object to provide a method of erasing memory cells with a shortened erasure time.
In order to accomplish these objects, a preferred method of erasing memory cells according to this invention begins by performing a first erasing operation on the memory cells and then determining which of the memory cells have threshold voltages less than a check voltage. Those cells with threshold voltages below the check voltage are identified as fast-erased memory cells. The fast-erased memory cells are then programmed to increase their threshold voltages. And finally, a main erasing operation is performed on all of the memory cells.
In other words, in the preferred method, a programming operation is performed on fast-erased memory cells during an erasure period. The identifying and programming of fast-erased cells increases the threshold voltages of those cells which would otherwise be regarded to as over-erased cells at the end of the erasure operation. By increasing the threshold voltages of the fast-erased cells, the uniformity of the erased threshold voltage distribution profile is enhanced.